1. Field of the Invention
Example embodiments of the present invention relate to semiconductor-on-insulator (SOI) structures, semiconductor devices using the same and methods of manufacturing the same, and more particularly, to a structure with a single-crystalline (for example, germanium (x-Ge)) layer on an insulating layer, semiconductor devices using the same, and methods of manufacturing the same.
2. Description of the Related Art
A germanium-on-insulator structure may be a semiconductor-on-insulator (SOI) structure with an insulating layer between a semiconductor material layer and a main substrate. Additionally, the semiconductor material layer may be formed of germanium.
A transistor with a conventional silicon-on-insulator (SOI) structure may have excellent switching speed and may be less influenced by a signal noise due to cosmic ray particles. Moreover, because an insulating gap may be provided between adjacent transistors a chip may be more highly integrated by narrowing insulating gap between the transistors and/or preventing a latch up between same.
FIG. 1 is a cross-sectional view of a thin film transistor 20 with a conventional SOI structure. Referring to FIG. 1, an insulating layer 11 may be formed on a silicon, glass or plastic substrate 10. A silicon channel layer 12 may be formed on the insulating layer 11. A doped source region 12a and a doped drain region 12b may be formed on the silicon channel layer 12. A gate insulator layer 13 may be formed on the silicon channel layer 12, and a gate 14 may be formed on the gate insulator layer 13. An interlayer dielectric (ILD) 15 may be formed on the gate 14. Through-holes of the ILD 15 may be formed on the region corresponding to a source electrode 16 and a drain electrode 17. The source electrode 16 may be connected to the source 12a of the silicon channel 12 and the drain electrode 17 may be connected to the drain 12b of the silicon channel 12.
In a transistor with an SOI structure, the switching speed becomes faster as the mobility of the semiconductor layer is increased. The mobility may depend on the type and the crystal structure of materials used. The mobility of a polycrystalline structure is higher than that of an amorphous structure. Also the mobility of a single-crystalline structure is higher than that of the polycrystalline structure. Additionally, the mobility of Ge is higher than that of Si. When using single-crystalline germanium (x-Ge), a transistor may have excellent switching speed.
Moreover, compared with silicon, germanium may require a lower manufacturing temperature for crystallization and also may be compatible with a system-on-panel (SOP) structure including a complementary metal-oxide semiconductor (CMOS) of a three-dimensional structure or a plastic substrate. Because germanium may be prone to have a low quality of native oxide and/or a larger gate leakage, when implementing, it has not been widely used in a metal-oxide semiconductor field effect transistor (MOSFET). However, germanium may be used in a GOI structure with a high-k gate insulator.
Conventionally, a wafer bonding process may be used. According to a so-called SmartCut™ conventional manufacturing method of forming a GOI structure, this conventional method includes forming a silicon/germanium alloy buffer layer with concentration gradient on a bare wafer with a constant thickness, forming a boundary layer of hydrogen dopant by injecting hydrogen ions (H+) on the buffer layer, forming a germanium layer and an etch-stop layer on the buffer layer, and exposing the germanium layer by polishing/etching processes after separating the boundary layer and bonding a wafer on a separate substrate. Such a conventional process is complex, time consuming and costly.